/* $Author: karu $ */
/* $LastChangedDate: 2009-03-04 23:09:45 -0600 (Wed, 04 Mar 2009) $ */
/* $Rev: 45 $ */

module sc( clk, rst, ctr_rst, out, err);

   input clk;

   input rst;

   input ctr_rst;

   output [2:0] out;

   output 	err;


      // your code
    wire [2:0]  CurState, NextState;
    wire reset = rst | ctr_rst;
    assign out = CurState;

    ctr_seq seq   (
        .CurState(CurState),
        .NextState(NextState),
        .clk(clk),
        .rst(reset) );
    ctr_comb comb (
        .CurState(CurState),
        .NextState(NextState)   );

endmodule // sc

// DUMMY LINE FOR REV CONTROL :1:
